DESCRIPTION OF THE RELATED ART
The process of generating a sine wave signal at a specified frequency is referred to as frequency synthesis. Frequency synthesis is an important component of many systems, including phased locked loop (PLL) systems. It can be done in analog fashion using a voltage controlled oscillator (VCO) or digitally with a numerically controlled oscillator (NCO). A VCO generates an analog sine wave at a frequency which is proportional to an input voltage level. An NCO outputs a digital sine wave at a frequency specified by an input digital word, and this process is known as direct digital synthesis or DDS. A D/A converter can be used to convert the digital sine wave to an analog signal if needed.
In the past, analog frequency synthesis systems were preferred to DDS systems because of their high output frequency capabilities and spectral purity. However, they also have exhibited severe limitations. For instance, they operate within a very small frequency range (typically less than one octave), they have a high sensitivity to temperature changes and aging, and they have long frequency tuning times (1 msec). Digital frequency synthesis techniques have solved these problems, but in the past have been expensive to implement. With the increasingly large die sizes used in ASIC technology, the cost of implementing customized digital frequency synthesizers has been dramatically reduced and are now routinely incorporated into larger system designs on ASIC chips. The advantages of DDS systems include fast switching times, smooth frequency transitions, and fine frequency steps.
The basic structure of an NCO comprises an N-bit accumulator register and a sine lookup table stored in ROM. The NCO uses the value in the accumulator register as an index into the lookup table. The lookup table has 2.sup.N entries corresponding to the 2.sup.N possible values that can be stored in the accumulator register, and the nth value in the table is the sine of the nth multiple of 2.pi./2.sup.N radians. In other words, the table represents one full cycle of a sine wave divided into 2.sup.N equally spaced values.
During operation, the value in the accumulator register is incremented at the accumulator clock rate f.sub.c. At the same rate, the NCO continuously outputs the lookup table entry corresponding to the value in the accumulator register. If the increment value is unity, then the accumulator runs through every value from 0 to 2.sup.N -1. This causes the NCO to reference every entry in the lookup table in order and output the sines of 2.sup.N angles between 0 and 2.pi., after which the accumulator overflows and starts again at the bottom of the table. Since there are 2.sup.N entries in the table, the output frequency f.sub.o of the NCO is equal to f.sub.c /2.sup.N.
The output frequency can be varied by changing the amount the accumulator is incremented each clock cycle. If the increment value is denoted by R, the output frequency can then be calculated by the equation: f.sub.o =R*(f.sub.c /2.sup.N). If R is increased, the frequency increases because the NCO skips entries in the lookup table and thereby runs through a full cycle of the sine wave more quickly. Thus, R is referred to as the frequency setting word. Because less table entries are accessed as R increases, an aliased frequency of f.sub.c -f.sub.o appears at the output when using a D/A converter to reconstruct the sine signal. This frequency must be filtered out using a low pass filter. Because of the cutoff frequency imposed by the filter, the maximum output frequency of the NCO is thus usually reduced to about 40% of f.sub.c.
Because the maximum output frequency is limited by the accumulator clock speed f.sub.c, NCO's using a single accumulator register cannot reach the high frequencies achieved by analog VCO's. The maximum clock rate f.sub.c of the accumulator is determined by the time it takes to update the state of the accumulator register. This depends on the speed of the N-bit adder including setup and hold times for the surrounding registers. Using one micron CMOS technology under worst operating conditions, a typical 16-bit NCO with a single accumulator can reach a maximum accumulator speed of only 65 MHz.
The most current solution to this problem is to use a pipelined structure for the accumulator. Instead of adding the frequency setting word R to the accumulator with an N-bit adder, the addition is performed one bit at a time by creating a pipeline with faster one-bit adders at each stage. This can increase the maximum frequency of the NCO by a factor near but usually less than N. Examples of pipelined architectures for NCO's can be found for example in the paper entitled "A 700-MHz 24-Bit Pipelined Accumulator in 1.2 .mu.m CMOS for Application as a Numerically Controlled Oscillator" in Proceedings of the 1991 IEEE Custom Integrated Circuits Conference and also in the paper entitled "A 150-MHz Direct Digital Frequency Synthesizer in 1.25 .mu.m CMOS with -90 dBc Spurious Performance" in 1991 IEEE International Custom Integrated Circuits Conference.
The disadvantage of using a pipelined accumulator is that it introduces a large latency into the system. Latency is defined as the number of clock cycles it takes for the output to respond to a change in the frequency setting word. Pipelined DDS systems have high latencies because it takes longer to increment the accumulator one bit at a time than all at once. The pipeline introduces a latency equal to the length of the pipeline as a tradeoff for speed. Examples of current pipelined systems include an NCO with a maximum clock frequency of 700 Mhz, but having a 55 clock cycle latency and an NCO with only a 13 cycle latency, but with a correspondingly low maximum clock rate of 150 MHz.
In some situations, latency is not a critical factor when using an NCO, but in many applications it is. For instance, if we were implementing a frequency tracking system using a phased locked loop, any delays in the response time of the NCO would affect response time of the system to changes in the incoming signal. In short, the latency determines the maximum frequency in the input signal to which the system will respond.